1. Field of the Invention
The present invention relates to a device for generating a clock signal.
2. Description of the Related Art
A plurality of circuits included in a server apparatus, such as an FT (Fault Tolerant) server, operate in accordance with clock signals. Due to this, the plurality of circuits operate synchronously with each other.
There is known a method of using a plurality of clock drivers, as a method of supplying clock signals to a plurality of circuits.
In this case, in order to synchronize the timings of the clock signals supplied from the plurality of clock drivers with each other, reset signals are applied to the plurality of clock drivers at the timing of starting the system, and at predetermined timings.
The plurality of clock drivers are reset at a same time by the reset signals. Thus, the timings of the clock signals supplied from the plurality of clock drivers are adjusted.
However, according to the above method, there is a problem that each time the plurality of clock drivers are reset, the system becomes unable to operate, and the system stops.
Accordingly, it is an object of the present invention to provide a clock signal generation device which adjusts the timings of clock signals without stopping the system.
To achieve the above object, a clock signal generation device according to the present invention is a device to and from which a plurality of clock generation units for generating clock signals can be attached and detached, and which comprises at least one clock generation unit,
wherein:
each of the plurality of clock generation units comprises
a clock driver which generates a clock signal in accordance with a reference clock, and
a supplying unit which supplies the reference clock to the clock driver;
the supplying unit supplies the clock driver, in a case where another clock generation unit is already attached to the clock signal generation device at a time the clock generation unit to which the supplying unit belongs is attached to the clock signal generation device, with a clock signal generated by the clock driver of the another clock generation unit as the reference clock during a predetermined first time; and
the clock driver makes a clock signal to be generated follow the supplied reference clock.
According to this invention, it is possible to adjust the timings of clock signals without stopping the system.
The supplying unit may supply the clock driver of the clock generation unit to which the supplying unit belongs, with a clock signal generated by the clock driver of the clock generation unit to which the supplying unit belongs as the reference clock, after the first time passes.
The supplying unit may comprise:
a control unit which outputs a control signal for selecting the reference clock from clock signals generated by the clock drivers of the clock generation units which are attached to the clock signal generation device; and
a selector circuit which selects one of clock signals generated by the clock drivers of the clock generation units which are attached to the clock signal generation device in accordance with the control signal, and supplies the selected clock signal to the clock driver as the reference clock.
The control unit may comprise:
a delay circuit which counts the first time; and
a control circuit which outputs the control signal to the selector circuit in accordance with a counting result of the delay circuit.
The delay circuit may supply a first level signal to the control circuit during the first time, and supply a second level signal to the control circuit after the first time passes.
The control circuit may output to the selector circuit, a control signal for controlling the selector circuit to select a clock signal generated by the clock driver of another clock generation unit, in a case where the control circuit is supplied with the first level signal and the another clock generation unit is attached to the clock signal generation device.
The control circuit may output to the selector circuit, a control signal for controlling the selector circuit to select a clock signal generated by the clock driver of the clock generation unit to which the control circuit belongs, in a case where the control circuit is supplied with the first level signal and no other clock generation unit is attached to the clock signal generation device.
The control circuit may output to the selector circuit, a control signal for controlling the selector circuit to select a clock signal generated by the clock driver of the clock generation unit to which the control circuit belongs, in a case where the control circuit is supplied with the second level signal.
The control unit may further comprise an adjusting unit which shuts off the second level signal supplied by the delay circuit, and instead supplies the first level signal to the control circuit during a predetermined second time. The adjusting unit may supply the first level signal to the control circuit during the second time, each time a predetermined third time passes.
The clock driver may comprise a PLL (Phase Locked Loop) circuit which makes the clock signal follow the reference clock.